1. Field of the Invention
The present invention relates to a holding circuit used in a pedestal level clamp circuit of video signal of a color television.
2. Related Art of the Invention
A holding circuit has a configuration in which a capacitor is charged with signal to be held. In the case where this capacitor is built in an integrated circuit, since its capacitance can not be increased above a certain degree, various contrivances are necessary to improve holding characteristics.
FIG. 1 is a holding circuit disclosed in Japanese Patent Application Laid-Open No. 64-78008. In FIG. 1, reference numeral 31 designates a differential amplifier in which emitters of two NPN transistors, 14, 15 are commonly connected on the ground side, and these emitters are connected with a ground line via a transistor 16 and a resistance 17 for switching. Serial circuit of a resistance 20, a transistor 21 and a resistance 22 connected with a power terminal 24 is a constant-current circuit. Bases of the transistors 21 and 16 are connected and a transistor 19 is connected between these bases and the ground line. Clamping pulse is inputted to a base 23 of the transistor 19, and when the clamping pulse is "L", the transistor 16 is turned on. A reference voltage Vref is applied to the base of the transistor 15 from a d.c. power source 18. To the base of the transistor 14, for example, video signal of NTSC are given from a terminal 1 via a resistance 2. A capacitor 9 is charged from the power terminal 24 via a resistance 10 and a transistor 11. A collector of the transistor 14 is connected with a resistance 13, and the connecting point is given to the base of the transistor 11. Transistors 6, 5 and 3 are in Darlington connection, and a circuit connecting the base of the transistor 6 to the capacitor 9 is a discharge circuit. An emitter 5 of a transistor 3 in the final stage is connected with the ground line via a resistance 4, and a collector is connected with the connecting point of the resistance 2 and the transistor 14, the connecting point serving as an output terminal 50 of a holding circuit.
Since the pedestal level of the video signal inputted is higher than the reference voltage Vref, when the clamping pulse is given and the transistor 16 is ON, current flows through the transistor 14, thereby the transistor 11 is turned on and the capacitor 9 is charged by the collector current. On the other hand, when the transistor 16 is OFF, the capacitor 9 is discharged through the discharge circuit of the transistor 6 and so on. By repeating such operations, voltages of the transistor 14 base or the output terminal 50 becomes equal to the reference voltage Vref.
As such, in Japanese Patent Application Laid-Open No. 64-78008, since impedance of the discharge circuit is increased by composing the discharge circuit of three transistors connected in Darlington Connection, a discharge time constant is large enough to compensate insufficient capacitance of the capacitor.
In such a holding circuit, a large charge time constant is also desirable. Namely, it is desirable to become reference voltage Vref by a few number of H of the video signal. This is because that if it is held at 1 or 2 H, the clamp level fluctuates by noises and images are unstable. Therefore, it may be considered to increase the resistance value of the resistance 10 in a charging circuit, but the large resistance can not be controlled precisely in the integrated circuit.
As another method, it may be considered to lengthen the charging time by reducing collector current of the transistor 11. For this purpose, the resistance value of the resistance 17 may be increased to reduce the current flowing through the transistors 14, 16. However, if it is arranged in such a manner, the switching operation of the transistor 16 becomes unstable and an accurate holding operation can not be accomplished.
Meanwhile, there are other problems as to the discharging circuit. In the case where noises are superposed on a video signal, there are cases in which the base potential or output voltage of the transistor 14 may become lower than the reference voltage Vref. When the output voltage becomes lower than the reference voltage Vref as such, current does not flow to the transistor 14 side, and not only the capacitor 9 is not charged, potential rise of the output terminal 50 delays due to the high discharge time constant. Namely, when the charge time constant is small and susceptible to the influence of noises, the large discharge time constant may cause inconveniences.
FIG. 2 shows a circuit in which another discharge route is added to solve such problems. Serial circuit of transistors 25, 26 is connected between the power terminal 1 and the ground line, and a collector of the transistor 15 is connected with the transistor 25 base. To the transistor 26, a transistor 27 is connected with form a Miller circuit therewith, and a collector of the transistor 27 is connected with a terminal of the capacitor 9.
When such a circuit is provided, the transistors 25, 26 are turned on when the transistor 15 is ON, and current same as those flowing through the serial circuit flows to the transistor 27 and serves as a discharge current of the capacitor, thereby the problems may be solved for the time being but the holding voltage fluctuates relatively violently, and when used in a pedestal clamp circuit, the stability of images is spoiled.